AT87251G2D-3CSUM【PDF 50/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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Sheet目录3833

46页 47页 48页 49页 [50页]51页 52页 53页 54页

AT/TSC8x251G2D

4135F–8051–11/06

AC Characteristics - SSLC: TWI Interface

Timings

Table 47.

TWI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of

100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-up

resistor, this must be < 1

μs.

3. Spikes on the SDA and SCL lines with a duration of less than 3TCLCL will be filtered

out. Maximum capacitance on bus-lines SDA and

SCL = 400 pF.

4. TCLCL = TOSC = one oscillator clock period.

Waveforms

Figure 18.

TWI Waveforms

Symbol

Parameter

INPUT

Min

Max

OUTPUT

Min

Max

THD; STA

Start condition hold time

14TCLCL(4)

4.0

μs(1)

TLOW

SCL low time

16TCLCL(4)

4.7

μs(1)

THIGH

SCL high time

14TCLCL(4)

4.0

μs(1)

TRC

SCL rise time

μs-(2)

TFC

SCL fall time

0.3

μs0.3 μs(3)

TSU; DAT1

Data set-up time

250 ns

20TCLCL(4)- TRD

TSU; DAT2

SDA set-up time (before repeated START

condition)

250 ns

μs(1)

TSU; DAT3

SDA set-up time (before STOP condition)

250 ns

8TCLCL(4)

THD; DAT

Data hold time

0 ns

8TCLCL(4) - TFC

TSU; STA

Repeated START set-up time

14TCLCL(4)

4.7

μs(1)

TSU; STO

STOP condition set-up time

14TCLCL(4)

4.0

μs(1)

TBUF

Bus free time

14TCLCL(4)

4.7

μs(1)

TRD

SDA rise time

μs

-(2)

TFD

SDA fall time

0.3

μs0.3 μs(3)

TSU;STA

TSU;DAT2

THD;STA

THIGH

TLOW

SDA

(INPUT/OUTPUT)

0.3 VDD

0.7 V

TBUF

TSU;STO

0.7 VDD

0.3 V

TRD

TFD

TRC

TFC

SCL

(INPUT/OUTPUT)

TSU;DAT1

THD;DAT

TSU;DAT3

START or Repeated START condition

START condition

STOP condition

Repeated START condition

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